Numerous electronic devices are widely used today, such as for example laptop computers, smartphones and tablets. Such electronic devices generally contain a microprocessor, volatile memory used by the microprocessor during the execution of software applications, and non-volatile memory for storing applications and data over the long term.
Read-amplifier circuits are used in a conventional manner in these volatile or non-volatile memory devices during the operations of reading the data in the memory cells of these devices.
Among the known read-amplifier circuit architectures, used in particular in non-volatile memories, may be cited the architecture comprising a memory element of the latch-memory type based on two inverters coupled in a crossed manner and intended to be connected between a pair of bit lines of the memory device.
More precisely, each inverter has its input connected to one bit line and its output connected to the other bit line.
Such a read-amplifier circuit provides fast signal amplification. However, in practice, it is difficult to produce a pair of inverters comprising perfectly matched transistors.
However, mismatches in the characteristics of the transistors can produce an offset voltage at the outputs of the inverters during a reset phase. Indeed, this offset is reflected at the inputs of the inverters.
However, in a particularly unfavorable case, this offset reflected at the level of the inputs of the inverters may be detected as a signal representative of a binary data item and consequently cause a reading error. Indeed, these data errors when reading are highly undesirable since they can negatively affect the performance of the electronic device.